Daily Archives: November 25, 2015

High speed real-time data caching and scheduling architecture based on microblaze and AXI on Xilinx FPGA

This high speed real-time data caching and scheduling architecture mainly design for high-speed data acquisition and real-time data processing system in radar, communication, radio astronomy, etc application.This architecture make use of the standard AXI bus and soft-core processor (Microblaze) to decouple the complex data caching and scheduling logic from RTL to general purpose processor. This architecture offers simplified API to PC (using PCIE interface) as well as soft processor (xilinx mircoblaze) to accomplish high complexity data caching and scheduling logic in large-scale high speed signal processing system.

Recently this architecture has been applied on a channel sounding system in the 5th mobile communications system conducted by HUAWEI. It works pretty well.

I designed the architecture and built a verification system. The system used one FPGA board (Xilinx KC705), and two ADC boards (ADI AD9361) in order to simulate the real time data stream loads. The FPGA project was developed through the latest Vivado IDE (version 2014.4). I reused some parts which is already verified in the project Distributed data acquisition system over long distance for radio astronomy telescope based on optical fiber. Including the PCI-Express interface, DDR3 Interface, DMA subsystem etc. These module were packaged into Vivado IP and used in this project.

Below is the block diagram of the architecture and the actual picture of the verification system.

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Figure 1 Block diagram of the high speed real-time data caching and scheduling architecture

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Figure 2  The actual picture of the verification system