Daily Archives: November 26, 2015


FPGA implementation of pulse signal detection and parameters measurement subsystem of a 24 channel synchronous digital receiver

1, Overview

The 24 channel broadband real-time synchronous digital receiver is the essential infrastructure of a passive direction finding and locating (DLS) system. The digital receiver system contained two 6U 13-Slot rackmount chassis. One is the synchronous acquisition subsystem which consisted 1 host PC board, 6 four channel signal acquisition (500Msps) board and 6 data transmission board. The other is the real-time signal processing subsystem which contained 1 host PC board and 6 data receive board and 6 signal processing board. The customized FPGA boards were all designed by the hardware team in my lab.

The synchronous acquisition subsystem sampled the 24 channel IF signal and cached the sampling data in the DDR2 memory in real time. The sampling data in each channel were divided in 12 time slots and then transmitted them to the real-time signal processing subsystem through the 6 transmission board. Each signal processing board received 2 time slots of 24 channel sampling data and conducted the signal processing (1 FPGA for 1 time slot). The block diagram (in board level) of the synchronous acquisition subsystem and the real-time signal processing subsystem are as follow.


Figure 1-1 Block diagram of the real-time signal processing subsystem in board level


Figure 1-2 Block diagram of the synchronous acquisition subsystem in board level

I was implemented the pulse signal detection and parameters measurement IP core which is the core DSP module of the real-time signal processing subsystem. The FPGA platform is XC5VSX95T-1FF1136 and the development environment is Xilinx ISE 12.3 and modelsim 6.5d. I also participated the entire debugging and testing process, including the broad level debugging ,system level debugging, system testing and the field testing.

Figure 1-3 is the actual picture of the four channel signal acquisition (500Msps) board. The signal processing board is the same except it didn't have 4 ADC chips. It contained 2 FPGA(XC5VSX95T-1FF1136) and 2 1GB DDR2 memory.


Figure 1-3 Actual picture of the four channel signal acquisition (500Msps) board

2, Detailed FPGA design and implementation

The pulse signal detection and parameters measurement subsystem contained 3 modules each packaged to a IP core. 1, signal detection module. 2, frequency measurement module. 3, time/phase difference measurement module. The processing frequency of these IP core are 200Mhz.

The signal detection module is the most sophisticated among the three modules. It had huge amount of computing logic and complex control logic. It detected the pulse signal in real time and measure the coarse pulse descriptor word (CPDW) of the pulse signal. The frequency measurement module and the time/phase difference measurement module used the CPDW to calculate the precise parameters of the pulse signal.

2.1, Signal detection module

The signal detection module contained three parts. 1, digital channelizer. 2, parameters coarse measurement. 3,CPDW filter. Figure 2-1 is the block diagram of the signal detection module.


Figure 2-1 Block diagram of the signal detection module

In the digital channelizer part, first the 24 channel input signal was processed by a simple narrow-band digital beamforming (weighted accumulation) module since the input signal are in X band (10GHz).  Then the beam data were processed by a digital channelizer (128 sub-channel). The input signal was frequency divided into 128 subbands. Then the output power spectrum (128 point FFT equivalent) was used to coarsely measure the pulse signal parameters. The coarsely measured parameters were packaged in to coarse pulse descriptor word (CPDW). At last, the CPDW was process through a CPDW filter module.  Figure 2-2 is the block diagram of the digital channelizer module (128 sub channels). Figure 2-3 is the block diagram of the pulse detector module. This module are new pulse signal detected and judgment module. Figure 2-4 is the block diagram of the parameter coarse measure module (PCM). There are two parallel PCM modules. The system can  simultaneously detect and measure two pulse signal (same arriving time, different freqency). The PCM module coarsely measure the frequency (128 point FFT equivalent), power, time of arrive (256ns), etc. And package them into a CPDW package.


Figure 2-2 Block diagram of the digital channelizer module

绘图3Figure 2-3 Block diagram of the new pulse detector module


Figure 2-4 Block diagram of the parameter coarse measure module

2.2, Frequency measurement module

The frequency measurement module were designed to calculate the precise frequency of the pulse signal detected. The input data are 1 channel data. It made use of the coarse frequency parameter (128 point FFT equivalent) in the CPDW calculate by the signal detect module and used a 9 bit local oscillator (LO) frequency to modulate the input signal to baseband. Then the modulated data are accumulated (accumulate data points are controlled by a 5 bit parameter). This is a equivalent discrete fourier transformation (DFT) calculation. And the DFT point can be controlled by the LO frequency parameter and the accum points parameter ranging from 2048 to 4096.

At last the different DFT results were sent into a peak search module to search the precise frequency of the pulse signal. If the pulse signal is a broadband signal the output frequency is the highest bin of the power spectrum. The precise frequency results were then used to calculate the time and phase difference of the different channel of the pulse signal. The block diagram of the frequency measurement module are as follow.


Figure 2-5 Block diagram of the frequency measurement module

2.3, Time/phase difference measurement module

The time/phase difference measurement module contained two main parts. 1, time difference measurement. In this part the 24 channel data were modulate to the baseband and then processed through a variable bandwidth filter (low pass) and a smoothing filter. And then the time difference of the 24 channel pulse signal were calculate through the threshold method.

2, phase difference measurement. In this part the data in each channel are calculate through frequency conversion (modulation) and accumulation which is also an equivalent DFT calculation. And then the result were sent to the phase difference calculate module to calculate the phase difference using the coordinate rotation digital computer (CORDIC) algorithm. Figure 2-6 is the block diagram of the time/phase difference measurement module.


Figure 2-6 Block diagram of the time/phase difference measurement module